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Link Layer IP Core

The New Wave Design and Verification Fibre Channel (FC) Link Layer core provides a complete IP solution for FC Layer 1 and Layer 2. The core includes all functionality needed to meet the framing and signaling specification of Fibre Channel including: comma alignment, 8b/10b encode/decode, primitive decode, scrambling, port state machine, credit manager, CRC generation/checking, elastic FIFO, and phase FIFO.

At the physical layer, the core is built for connecting to ASIC/FPGA embedded SERDES or discrete SERDES parts. The user interface of the core provides an intuitive streaming interface for application designers. The user interface within the core also includes cross clocking logic making integration into the larger design extremely simple.

This core has been used on a diverse set of applications, from enterprise storage to aerospace electronics, and on a wide range of parts at varying operating operating rates. The core comes with test-benches and example code, making design integration a straightforward task.

Get This IP Core Pre-Loaded on the Following FPGA Cards:
V1141 (Quad-Port)     V1151 (Quad-Port)     V1152 (12-Port)     V5051 (Quad-Port)     V5052 (16-Port)