Mil1394 GP2Lynx Link Layer Controller IP Core
The New Wave DV 1394b GP2Lynx Link Layer IP Core provides a complete IP solution for the GP2Lynx Link Layer of the 1394 protocol.
The Core includes all functionality needed to meet the AS5643 specification including: Asynchronous Transmit, Isochronous Receive, STOF handling, STOF regulated transmit functions, and CRC generation/checking.
At the PHY-Link interface, the Core is built for connecting to any PHY implementing the defined standard PHY-Link interface. This interface is compatible with the New Wave DV PHY IP core as well as discrete PHY Layer integrated circuits.
This General Purpose IEEE-1394 Link Layer Controller (LLC) core is targeted towards aerospace and defense and has been used on a wide range of FPGAs at varying operating data rates. The Core comes with test-benches and example code, making design integration a straightforward task.
Evaluation versions of the GP2Lynx Link Layer IP Core are available and New Wave DV has a set of standard form factor boards featuring FPGAs, 1394b connectors and transformers, and off-the-shelf reference designs for quick evaluation of the IP core.
- AS5643 compliant interface with hardware-based STOF offload
- Supports S100/S200/S400 data rates
- Configurable number of GP2Lynx nodes in a single FPGA
- Legacy microprocessor or AXI host interface available
- Standard PHY-Link interface supports integration with PHY IP core or external PHY device
- Increased interface port density while reducing interface size and power
- Increased performance with hardware-based AS5643 offload
- Additional diagnostics and programmable operation features
- Leverage proven technology for standard interface implementation
AMD (Xilinx): Virtex, Kintex, Artix, Zynq FPGAs
Intel (Altera): Stratix, Arria, Cyclone FPGAs
Microchip (Microsemi): SmartFusion2, Igloo2 FPGAs
- Vehicle System – Remote Node
- Vehicle System – Vehicle Management Computer
- Avionic Mission Systems