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Mil1394 AS5643 Link Layer Controller IP Core

The New Wave Design Mil1394 AS5643 Link Layer Controller IP Core (Offload Engine) provides a complete hardware IP solution for the 1394 AS5643 protocol.

The Offload Engine provides hardware-based AS5643 message label filtering, hardware mapping of AS5643 message label to host memory, and complete offload of Mil1394 message handling including: Asynchronous Transmit, Isochronous Receive, STOF receive/transmit handling, STOF regulated transmit functions, Self ID operations, vertical parity, and CRC generation/checking.

The host interface to the core can be AXI or PCIe. The core is built for dropping into an FPGA and providing the complete design from processor interface to Mil1394 network interface.

This core is targeted toward applications in aerospace and has been used on a wide range of parts at varying operating rates. The core comes with test-benches and example code, making design integration a straightforward task.

Evaluation versions of the Offload Engine are available and New Wave Design has a set of standard form factor boards featuring FPGAs, 1394b connectors and transformers, and off-the-shelf reference designs for quick evaluation of the IP core.

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Mil1394 AS5643 Link Layer Controller IP Core Overview

The New Wave Design Mil1394 AS5643 Link Layer Controller IP Core (Offload Engine) provides a complete hardware IP solution for the 1394 AS5643 protocol.

The Offload Engine provides hardware-based AS5643 message label filtering, hardware mapping of AS5643 message label to host memory, and complete offload of Mil1394 message handling including: Asynchronous Transmit, Isochronous Receive, STOF receive/transmit handling, STOF regulated transmit functions, Self ID operations, vertical parity, and CRC generation/checking.

The host interface to the core can be AXI or PCIe. The core is built for dropping into an FPGA and providing the complete design from processor interface to Mil1394 network interface.

This core is targeted toward applications in aerospace and has been used on a wide range of parts at varying operating rates. The core comes with test-benches and example code, making design integration a straightforward task.

Evaluation versions of the Offload Engine are available and New Wave Design has a set of standard form factor boards featuring FPGAs, 1394b connectors and transformers, and off-the-shelf reference designs for quick evaluation of the IP core.

Get This IP Core Pre-Loaded on the Following FPGA Cards:
V1142 (4-Port)    V1144 (12-Port)    V1146 (9-Port)    V5054 (30-Port)

Mil1394 AS5643 Link Layer Controller IP Core Features

  • AS5643-compliant interface with hardware-based STOF offload
  • Hardware DMA engines with message label mapped buffers
  • STOF transmitter and receiver hardware functions
  • Supports S100/S200/S400 data rates
    Configurable number of nodes and ports in a single FPGA
  • AXI-based host interface for embedded or PCIe-based processors

Mil1394 AS5643 Link Layer Controller IP Core Applications

  • Vehicle System – Remote Node
  • Vehicle System – Vehicle Management Computer
  • Avionic Mission Systems

Mil1394 AS5643 Link Layer Controller IP Core Benefits

  • Increased performance with hardware-based AS5643 offload
  • Hardware-based message label filtering and host DMA setup
  • Additional diagnostics and programmable operation features
  • Leverage proven technology for standard interface implementation
  • Hardware offload moves strict AS5643 timing from software to hardware

Mil1394 AS5643 Link Layer Controller IP Core Overview

The New Wave Design Mil1394 AS5643 Link Layer Controller IP Core (Offload Engine) provides a complete hardware IP solution for the 1394 AS5643 protocol.

The Offload Engine provides hardware-based AS5643 message label filtering, hardware mapping of AS5643 message label to host memory, and complete offload of Mil1394 message handling including: Asynchronous Transmit, Isochronous Receive, STOF receive/transmit handling, STOF regulated transmit functions, Self ID operations, vertical parity, and CRC generation/checking.

The host interface to the core can be AXI or PCIe. The core is built for dropping into an FPGA and providing the complete design from processor interface to Mil1394 network interface.

This core is targeted toward applications in aerospace and has been used on a wide range of parts at varying operating rates. The core comes with test-benches and example code, making design integration a straightforward task.

Evaluation versions of the Offload Engine are available and New Wave Design has a set of standard form factor boards featuring FPGAs, 1394b connectors and transformers, and off-the-shelf reference designs for quick evaluation of the IP core.

Get This IP Core Pre-Loaded on the Following FPGA Cards:
V1142 (4-Port)    V1144 (12-Port)    V1146 (9-Port)    V5054 (30-Port)

Mil1394 AS5643 Link Layer Controller IP Core Features

  • AS5643-compliant interface with hardware-based STOF offload
  • Hardware DMA engines with message label mapped buffers
  • STOF transmitter and receiver hardware functions
  • Supports S100/S200/S400 data rates
    Configurable number of nodes and ports in a single FPGA
  • AXI-based host interface for embedded or PCIe-based processors

Mil1394 AS5643 Link Layer Controller IP Core Applications

  • Vehicle System – Remote Node
  • Vehicle System – Vehicle Management Computer
  • Avionic Mission Systems

Mil1394 AS5643 Link Layer Controller IP Core Benefits

  • Increased performance with hardware-based AS5643 offload
  • Hardware-based message label filtering and host DMA setup
  • Additional diagnostics and programmable operation features
  • Leverage proven technology for standard interface implementation
  • Hardware offload moves strict AS5643 timing from software to hardware

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