1394b AS5643 IP Core
The New Wave Design and Verification (New Wave DV) 1394b AS5643 IP core provides a complete hardware IP solution for the 1394b AS5643 protocol.
The core provides hardware based AS5643 message label filtering, hardware mapping of AS5643 message label to host memory, and complete offload of 1394 AS5643 message handling including: Asynchronous Transmit, Isochronous Receive, STOF receive/transmit handling, STOF regulated transmit functions, Self ID operations, vertical parity, and CRC generation/checking.
The host interface to the core can be AXI or PCIe. The core is built for dropping into an FPGA and providing the complete design from processor interface to 1394b AS5643 network interface.
Get This IP Core Pre-Loaded on the Following FPGA Cards:
V1142 (4-Port) V1144 (12-Port) V1146 (9-Port) V5054 (30-Port)
Features
- AS5643 compliant interface with hardware based STOF offload
- Hardware DMA engines with message label mapped buffers
- STOF transmitter and receiver hardware functions
- Supports S100/S200/S400 data rates
- Configurable number of nodes and ports in a single FPGA
- AXI-based host interface for embedded or PCIe based processors
Benefits
- Increased performance with hardware-based AS5643 offload
- Hardware-based message label filtering and host DMA setup
- Additional diagnostics and programmable operation features
- Leverage proven technology for standard interface implementation
SpecificationsSpecs
| Supported Devices |
Xilinx: Virtex, Kintex, Artix FPGAs Intel (Altera): Stratix, Arria, Cyclone FPGAs Microsemi: SmartFusion2, Igloo2 FPGAs |
| Supported Rates |
S100/S200/S400 |
| Operating Frequencies |
S100: 12.288Mhz S200: 24.576MHz S400: 49.152MHz |
Applications App
- Avionics vehicle and mission systems
- Industrial/Machine vision systems
Documentation Doc
| Datasheet | 1394b-AS5643-IP-Core-Datasheet |
| Block Diagram | 1394b-AS5643-Block-Diagram |