IP Cores

New Wave DV IP Cores can be provided pre-loaded on New Wave DV’s boards to provide a turn-key solution. They are also available stand-alone for your custom hardware needs.

Choose your IP Core or Protocol below to learn more:

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  FC Link Layer (LL) IP Core

  The Fibre Channel (FC) Link Layer core provides a complete IP solution for FC-1 and FC-2 layers. More >

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  FC Anonymous Subscriber Messaging (ASM) IP Core

  Hardware-based full-network stack implementation of FC-AE-ASM. Provides hardware-based label lookup, DMA controllers, and message chain engines. F-35 compatible interface mode available More >

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  FC Upper Layer Protocol (ULP) IP Core

  Hardware-based full-network stack implementation of FC-AE-RDMA or FC-AV. Provides hardware-based buffer mapping, DMA controllers, and message chain engines. F-18/F-15 compatible interface mode available. More >

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  1394b PHY IP Core

  AS5643 PHY layer hardware implementation. Includes standard PHY-Link interface. More >

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  Mil1394 OHCI Link Layer Controller IP Core

  Mil1394 OHCI Link layer hardware implementation. Includes standard PHY-Link interface and AXI bus for PCIe or embedded processor interface. More >

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  Mil1394 GP2Lynx Link Layer Controller IP Core

  Mil1394 GP2Lynx Link layer hardware implementation. Includes standard PHY-Link interface. More >

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  Mil1394 AS5643 Link Layer Controller IP Core

  Hardware-based full-network stack implementation of AS5643. Provides hardware based label lookup, DMA controllers, and message chain engines. F-35 compatible interface mode available. More >

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  Serial Front Panel Data Port (sFPDP) IP Core

  The sFPDP core provides a complete hardware implementation of the ANSI/VITA 17.1-2015 specification supporting full-bandwidth operation with an easy to integrate frame interface. More >

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  ARINC-818 IP Core

  The ARINC-818 core provides a complete hardware IP solution for the ARINC-818 protocol. More >

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  ARINC 818 Direct Memory Access (DMA) IP Core

  Provides a complete hardware IP solution for the receipt and transmission of the ARINC 818 protocol. Optimized for embedded applications and offloads formatting, timing, and buffer management of the ARINC 818 link. More >

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  ARINC 818 Streaming IP Core

  Provides a real-time streaming conversion from a pixel bus into an ARINC 818 formatted FC serial data stream, or from ARINC 818 formatted FC data into a pixel bus. More >

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  HOTLink II IP Core

  Complete layer 2 hardware implementation for HSI. Provides easy to integrate frame interface. Supports full-rate, ½ rate, and ¼ rate operation as specified by the standard. F-18 compatible interface implementation. More >

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  High Speed Data Bus (HSDB) IP Core

  Complete PHY and Mac layer hardware implementation for HSDB. Provides easy to integrate frame interface. F-22 compatible interface implementation. More >