NI PXIe-6593 Serial RapidIO® Protocol Endpoint Offload
Available on the National Instruments 6593 card, the SRIO Endpoint Offload has two fully functional and independent SRIO endpoints. Each SRIO port is automatically managed and maintained by the FPGA and requires no host/software interaction. The FPGA updates and maintains its memory bank (2GB per port) based on SRIO transactions.
The port memory can be accessed asynchronously at any time by the host. The design provides a way to have a SRIO device completely integrated into LabVIEW™ without the software overhead of maintaining the link. The endpoint processes and responds to requests without host/ software intervention. The on-board memory is updated with incoming NWRITE, SWRITE, Data Streaming, Doorbell, and Message packets. NWRITE and SWRITE operations are stored at the addressed location while Doorbell, Message, and Data Streaming packets are stored in a circular buffer. Responses to received NREAD requests return the data from the addressed location of the on-board memory.
Packet generation can be configured to be regular and periodic (hardware offload mode) or driven by the host software. When in hardware offload mode, data generation is handled by a scripting-based hardware offload engine. The user defines a script that determines the format and timing of any data transmission. The script is executed completely in hardware which gives the user a very high degree of precision and control in creating data transmission patterns. Optionally, the system can be operated as a standalone instrument and controlled remotely via a network connection. Command and control is handled via plain text UDP commands which allows integration into test systems running C#, C++, Python, and more.
Can be combined with the SRIO Data Recorder functionality into a single design.
- Windows C or LabVIEW™ API. Example designs provided
- Example Python API for remote command and control of the host application
- Statistical eye diagrams for signal integrity measurements
- Error monitoring and tracking
- Full hardware offload of SRIO endpoint
- Flexible test configuration with software/LabVIEW™ control of test instrument
- Complete FPGA design with FPGA-based offload of protocol. No FPGA design needed by user
- Reduce development time by focusing on software test applications instead of test hardware development
- Lower total cost of test development and test system operation
Fully compatible and integrated into LabVIEW™
2 independent SRIO ports via QSFP connectors
1x, 2x, 4x lane modes at 1.25, 2.5, 3.125, 5 Gbps
Supports 8-bit or 16-bit device IDs
2GB memory per SRIO port
Up to 2 ports using QSFP connectors
- LabVIEW™ integrated SRIO host or endpoint
- Script-based data generation for emulation of sensors and systems